The invention is in the field of transistor amplifier circuits, and relates more particularly to a Class C power amplifier circuit having a dynamic biasing circuit for linearizing the amplifier.
Amplifiers of this general type are frequently used in such applications as high-frequency RF amplifiers, such as those used in wireless communications devices. In order to obtain the desired linear input-output characteristic, the output stage is typically operated in Class B or Class AB. Although it would be desirable to operate the output stage in Class C in order to benefit from the higher efficiency obtainable in this mode, this has not heretofore been possible when a linear amplifier characteristic is also desired, due to the inherent nonlinearity of the Class C mode.
A technique for boosting amplifier bias to achieve optimum maximum power output level and reduced power dissipation at low power levels in a Class B or Class AB amplifier circuit is disclosed in U.S. patent application Ser. No. 09/536,946, filed Mar. 28, 2000, by Sifen Luo and the present inventor. That invention is directed to boosting a bias signal to maintain linear operation in Class B or Class AB, but does not enable linear operation in the more-efficient Class C mode of operation.
Accordingly, it would be desirable to have a power amplifier circuit which offers the advantage of higher efficiency inherent in Class C operation, while at the same time providing a substantially linear input-output relationship similar to that of a Class B amplifier.
It is therefore an object of the present invention to provide a power amplifier circuit which provides the advantage of higher efficiency inherent in Class C operation, while at the same time providing a substantially linear input-output relationship similar to that of a Class B amplifier.
In accordance with the invention, this object is achieved by a new power amplifier circuit for amplifying an input signal and having a conduction angle of less than about 180xc2x0. The circuit includes an amplifying transistor and a dc bias circuit for biasing the amplifying transistor to obtain the desired conduction angle. The dc bias circuit includes a dynamic biasing circuit for decreasing a dc bias signal provided to the amplifying transistor as the input signal to the power amplifier circuit increases.
In a preferred embodiment of the invention, the power amplifier circuit is a linearized Class C amplifier circuit.
In a further preferred embodiment of the invention, the amount of decrease in the dc bias signal is proportional to the amount of increase in the amplitude of the input signal. Assuming a piecewise linear transistor characteristic for simplicity, this proportionality factor becomes equal to the cosine of the desired conduction angle divided by two.
In yet a further preferred embodiment of the invention, the conduction angle is maintained substantially constant with variations in input signal amplitude.
A power amplifier in accordance with the present invention offers a significant improvement in that two previously mutually-exclusive features, namely high efficiency and substantially linear operation, can be achieved in a single circuit.
These and other aspects of the invention will be apparent from and elucidated with reference to the embodiments described hereinafter.